As technology advances in designing integrated circuit (IC) chips, such as FDSOI (Fully Depleted Silicon-on-Insulator) devices, problems develop as the elements formed on the IC chips are required to become smaller and smaller. For example, in FDSOI technology, a problem arises if contacts, such as source/drain contacts, are directly connected over Shallow Trench Isolation (STI) regions to metal lines, such as power supply rails connected to a plurality of individual semiconductor devices connected to the source/drain contacts. In such structures, shorts are likely to occur between the contacts and the substrate in the areas where the contacts extend over the STI regions. This happens because the contacts for the transistor regions (e.g., in FDSOI devices) and for the source/drain regions are formed with the same etching mask, which makes the etching process difficult to control. Thus, punch through to the substrate can occur.
One solution has been to limit the contacts to only over the source/drain regions, such that they do not extend over the STI. In this solution metal tabs are used at a higher level than the source/drain contacts to connect between the source/drain contacts and adjacent common metal lines, e.g., power supply rails. In other words, the metal tabs extend over the STI regions which surround the source/drain regions, rather than the source/drain contacts themselves extending over the STI region. This helps to avoid short circuits to the substrate because the metal tabs are located at a higher level above the STI regions than the source/drain contacts, so punch through to the substrate is not likely to occur, even at tighter tolerances.
This solution works well for relaxed pitches, but problems can still exist for tighter pitches. For example, as smaller pitches between the metal tabs are used, problems in excessive variation of the process variation (PV) band become a printing concern. The PV band variation correlates to how the lines formed by lithography will actually print. As metal tabs become closer together due to smaller pitches required for smaller devices, the variation of the PV band can become much larger than its acceptable range. For example, the PV band variation for pitches of 22 nm or less between adjacent metal tabs on the same metallization level is unacceptable since the manufactured contacts might overlay edges of the source/drain regions, resulting in shorts.
Another constraint from the design side is that it is very hard to decide apriori if a tab is going to be used as a metal tab at a first metallization level or as a via at a second metallization level. In other words, because of cell placement, it is difficult to predict if the adjacent cell will have a metal tab or a via tab.